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MCP2515
FIGURE 6-1:
ERROR MODES STATE DIAGRAM
RESET
REC < 127 or
Error-Active
TEC < 127
128 occurrences of
11 consecutive
Error-Passive
REC > 127 or
TEC > 127
TEC > 255
Bus-Off
“recessive” bits
REGISTER 6-1:
TEC – TRANSMIT ERROR COUNTER
(ADDRESS: 1Ch)
R-0
TEC7
R-0
TEC6
R-0
TEC5
R-0
TEC4
R-0
TEC3
R-0
TEC2
R-0
TEC1
R-0
TEC0
bit 7
Legend:
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
TEC<7:0>: Transmit Error Count bits
REGISTER 6-2:
REC – RECEIVER ERROR COUNTER
(ADDRESS: 1Dh)
R-0
REC7
R-0
REC6
R-0
REC5
R-0
REC4
R-0
REC3
R-0
REC2
R-0
REC1
R-0
REC0
bit 7
Legend:
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
REC<7:0>: Receive Error Count bits
DS21801G-page 48
? 2003-2012 Microchip Technology Inc.
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